Prior art computer aided design (CAD) software is known to include complimentary tool suites for designing and analyzing the package of a die, e.g., a microprocessor. A “package” is the physical interconnection between the die and, for example, a printed circuit board (PCB). A typical package has several interconnected layers between its top level (L1), which connects to the die, and its bottom level (L2), which connects to the PCB.
A package “design” is a hierarchical and symbolic digital model of the package circuit. Those skilled in the art appreciate that hardware description languages (HDLs) may be used to formulate this digital model. The digital model consists of linked design elements that simulate the package circuit. The design elements are for example digital representations of the transistors, resistors, logic gates, traces (i.e., intra-level conductors), capacitors, vias (i.e., inter-level connectors), and wire bonds that make up the simulated schematic circuit.
The design elements and interconnections are collated and defined in a design database, which is a textual representation of the package design. The design database may further describe the package design in terms of higher-level cells consisting of two or more design elements, and the connections between cells. Each “net” in the package design describes the linked conductors (e.g., traces of a level and vias between levels) that form a circuit between an input and an output of the package. The CAD software may automatically route traces within a given level of the package design; it may further automatically route traces in a level and between vias of the package design.
The design database is processed by the CAD software to perform circuit simulation. The CAD software is for example used to model a signal through the package and over a net (i.e., a “signal net”). Substrate laminate technologies and bond interconnections may also be evaluated through the CAD software.
One exemplary prior art CAD software is Advanced Package Designer (APD) from Cadence Design Systems, Inc., of San Jose, Calif. Such CAD software is known to include verification procedures and dynamic feedback that evaluate design accuracy against a set of physical and electrical design rules, or constraints. Physical design constraints help to ensure manufacturability; electrical design constraints help to ensure electrical specifications of the design. By way of example, this CAD software generates a Design Rule Check (DRC) indicating whether the design meets the various constraints. The prior art CAD software also provides a graphical user interface to view all or part of the package design in two dimensions, for example in a flat or perspective rendition, or with levels overlaid relative to one another.
FIG. 1 illustrates one prior art system 10 for designing a package with prior art CAD software 12. CAD software 12 is stored within a computer 14, initially within a storage unit 16. A processor 18 of computer 14 operates CAD software in response to user inputs at an input interface 20 (e.g., a computer keyboard and mouse). As those skilled in the art appreciate, when initialized, CAD software 12 may also load into internal memory 22 of computer 14. A human designer at input interface 20 then controls CAD software 12, through processor 18, to create a package design 24, also stored within memory 22. The designer can command processor 18 and CAD software 12 to graphically show package design 24 at a graphical user interface 26 (e.g., a computer monitor) of system 10. Illustratively, package design 24 is graphically depicted on a display 28 of graphical user interface 26 as a five-level package model 24A shown in FIG. 2.
FIG. 2 illustrates detail of graphical model 24A. L1 of model 24A couples with a die, and L2 of model 24A couples with a PCB. Levels I(1), I(2) and I(3) of model 24A represent intermediate levels of package design 24. Levels L1, I(1), I(2), I(3), L2 are shown as distinct elements and without proper or to-scale orientation for ease of illustration. An illustrative signal net 30A is shown from an input connector 32A to an output connector 34A of model 24A. Signal net 30A traverses design elements in the form of traces and vias between connectors 32A, 34A: via 35A from connector 32A of L1 to trace 36A of I(1); trace 36A within I(1) from via 35A to via 38A; via 38A from trace 36A of I(1) to trace 40A of I(2); trace 40A within I(2) from via 38A to via 42A; via 42A from trace 40A of I(2) to trace 44A of I(3); trace 44A within I(3) from via 42A to via 46A, which terminates at connector 34A of L2.
Another signal net 30B is shown from an input connector 32B to an output connector 34B of model 24A. Signal net 30B traverses design elements in the form of traces and vias between connectors 32B, 34B: via 35B from connector 32B of L1 to trace 36B of I(1); trace 36B within I(1) from via 35B to via 38B; via 38B from trace 36B of I(1) to trace 40B of I(2); trace 40B within I(2) from via 38B to via 42B; via 42B from trace 40B of I(2) to trace 44B of I(3); trace 44B within I(3) from via 42B to via 46B, which terminates at connector 34B of L2.
With further regard to FIG. 1, CAD software 12 is also operable to generate a design database 50. In one example, design database 50 textually defines signal nets 30A and 30B of FIG. 2: signal net 30A is defined by connectors 32A, 34A, traces 36A, 40A, 44A, and vias 35A, 38A, 42A, 46A; signal net 30B is defined by connectors 32B, 34B, traces 36B, 40B, 44B, and vias 35B, 38B, 42B, 46B. Design database 50 also includes parameters (often called a “netlist”) to set physical package dimensions and to ensure that signal nets 30A and 30B have start and end points (i.e., connectors 32A, 34A for signal net 30A, and connectors 32B, 34B for signal net 30B). A designer can manipulate design database 50 to develop the desired package design 24.
CAD software 12 utilizes design rules 52 to generate one or more DRCs 54 in the event that a design element or signal net of package design 24 exceeds a manufacturing constraint or electrical specification. By way of example, design rules 52 may specify that a trace width of trace 36 is 20 μm, to ensure manufacturability. If a designer of package 24 implements trace 36A with 10 μm, for example, then CAD software 12 generates a DRC 54A, which may be graphically displayed on model 24A, as shown in FIG. 2. The user is thus made aware that a problem may exist with trace 36A.
Those skilled in the art appreciate that package design 24 often has more than the five levels illustrated in model 24A; however only five levels are shown in FIG. 2 for ease of illustration. For example, it is common that package design 24 include ground levels between each level with signal traces (I(1), I(2) and I(3); however these ground levels are not shown to simplify illustration. Those skilled in the art also appreciate that package design 24 also typically has many more signal nets and other design elements than illustrated signal nets 30A and 30B. For example, package design 24 typically includes many other traces and vias (not shown) within package model 24A.
Signal nets 30A, 30B are also illustrated close together with substantially similar form (e.g., traces 40A, 40B are substantially parallel) to illustrate that signal net pair 30A, 30B operates to transfer differential signals through package design 24. As those skilled in the art appreciate, differential signals provide benefits to electronic circuits, for example to provide enhanced signal discrimination, to reduce susceptibility to interference, and/or to accurately process bipolar signals. FIG. 2 also illustrates that traces of signal nets 30A, 30B sometimes deviate from one another within a given level. For example, in level I(1), trace 36B has four trace deviations 50 forming trace segments 36B(1)–36B(4), while trace 36A has one trace deviation 50 forming trace segments 36A(1) and 36A(2). Another deviation between signal nets 30A, 30B also clearly occurs in level I(3). In I(3), trace 44B has three trace deviations 50 forming trace segments 44B(1)–44B(3), while trace 44A has one trace deviation 50 forming trace segments 44A(1), 44A(2).
FIG. 3 illustrates package model 24A in a side view. FIG. 3 further illustrates how package design 24 connects between a die 80 and a PCB 82. Connector 32A is for example a pad that connects with a solder ball 84A of die 80; connector 34A is for example a pad that connects with signal wires of PCB 82. Similarly, connector 32B is for example a pad that connects with a solder ball 84B of die 80; connector 34B is for example a pad that connects with signal wires of PCB 82. As shown, signal nets 30A, 30B illustrate an exemplary pair of conductors suitable for transferring a differential signal from die 80 to PCB 82. Trace deviations 50 are not shown in FIG. 3 since they occur within a given layer.
The increased complexity of the modem die has correspondingly increased the complexity of the package design. An example of a complex die includes a Precision Architecture—Reduced Instruction Set Computer (PA-RISC) processor produced by Hewlett Packard Corporation, which has over one billion components. The package for the PA-RISC processor must maintain high signal integrity through its signal nets; this is especially true when the signal integrity involves differential signals. However the prior art CAD software does not simulate this signal integrity as required by the corresponding die. Accordingly, the package may be physically manufactured, at great expense, before the designer learns that the package is not suitable for operation with the die. More particularly, though the DRCs generated by the prior art CAD software may assist in manufacturability; they do not, however, warn the designer of signal net incompatibilities between the die and the package. In one example, prior art CAD software 12 does not evaluate the spacing or signal coupling between a pair of traces designed to carry differential signals of the package; if this spacing varies too much, the differential signal can decouple within the layer and induce common mode noise or other undesirable artifacts.